View AK8181H_7826828.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

AK8181H draft - e - 02 feb - 2013 - 1 - features ten differential 2.5v, 3.3v lvpecl outputs two selectable differential inputs pclk x p/ n pair s can accept the following differential input levels; lvpecl, lvds, lvhstl , sstl, h csl clock output frequency up to 70 0 mhz translates any single - ended input signal to 3.3v lvpecl levels with resistor bias on pclk x n input o utput skew : 30 ps typical part - to - part skew : 340 ps maximum propagation delay : (t.b.d) n s maximum add itive phase jitter(rms) : 0.0 4 5 ps (typical) operating temperature range: - 4 0 to +85 package: 32 - pin lqfp (pb free) pin compatible with ics853 10 i - 01 description the ak 8181 h is a member of akm s lvpecl clock fanout buffer family designed for telecom, networking and computer applications , requiring a ra nge of clocks with high performance and low skew . the ak 8181h distributes 10 buffered clocks . ak 8181 h are derived f r o m akm s long - term - experienced clock devic e technology , and enable clock output to perform low skew . the ak 8181 h is ava ilable in a 32 - pin lqfp pa ckage. block di agram 2.5v, 3.3v lvpecl 1: 10 preliminary clock fanout buffer ak 8181 h
AK8181H feb - 2013 draft - e - 02 - 2 - pin d escription s package: 32 - pin lqfp (top view) pin no. pin name pin type pullup down description 1 , 9, 16, 25, 32 v dd pwr --- positive power supply 2 clk_se l in pull down clk select input (lvcmos/lvttl) pin is connected to vss by internal resistor. (typ. 5 1 k ? ? high: selects pclk1p/n inputs low (open): selects pclk0p/n inputs 3 pclk0p in pull down non - inverting differential clock input pin is connected to vs s by internal resistor. (typ. 51 k ? ? ? *when using pclk1 input (clk_sel=high), it shou ld be connected to vss or opened. ? 4 pclk0n in pull up i nverting differential clock input pin is connected to vdd by internal resistor. (typ. 5 1 k ? ? *when using pclk1 input (clk_sel=high), it should be connected to vdd or opened. 5 nc --- no connect 6 pc lk1p in pull down non - inverting differential lvpecl clock input pin is connected to vs s by internal resistor. (typ. 51 k ? ? ? *when using pclk0 input (clk_sel=low), it should be connected to vss or opened. ? 7 pclk1n in pull up i nverting differential clock inpu t pin is connected to vdd by internal resistor. (typ. 5 1 k ? ? ? *when using pclk0 input (clk_sel=low), it should be connected to vdd or opened. 8 v ss pwr --- negative power supply
AK8181H draft - e - 02 feb - 2013 - 3 - pin no. pin name pin type pullup down description 10, 11 q9n, q9 out --- differential clock output (lvpecl/ecl) 12, 13 q8n, q8 out --- differential clock output (lvpecl/ecl) 14, 15 q7n, q7 out --- differential clock output (lvpecl/ecl) 17, 18 q6n q6 out --- differential clock output (lvpecl/ecl) 19, 20 q5n, q5 out --- diffe rential clock output (lvpecl/ecl) 21, 22 q4n, q4 out --- differential clock output (lvpecl/ecl) 23, 24 q3n, q3 out --- differential clock output (lvpecl/ecl) 26, 27 q2n, q2 out --- differential clock output (lvpecl/ecl) 28, 29 q1n, q1 out --- different ial clock output (lvpecl/ecl) 30, 31 q0n, q0 out --- differential clock output (lvpecl/ecl) ordering information part number marking shipping packaging package temperature range ak818 1 h ak 81 81 h tape and reel 32 - pin lqf p - 4 0 to 85 c
AK8181H feb - 2013 draft - e - 02 - 4 - absolute maxim um rating over operating free - air temperature range unless otherwise noted (1) items s ymbol ratings unit s upply v oltage (2) v dd - 0.3 to 4.6 v input voltage (2) vin v ss - 0. 3 to v dd +0. 3 v input c urrent (any pins except supplies) i in 1 0 ma storage tempera ture tstg - 55 to 1 5 0 ? c note (1 ) stress beyond those listed under absolute m ax imum r atings may cause perman ent damage to the device. these are stress ratings only. f unctional operation of the device at these or any other conditions beyond those indicat ed under recommended operating conditions is not implied. exposure to absolute - maximum - rating conditions for extended periods may affect device reliability. electrical par ameters are guaranteed only over the recommended operating temperature range. (2) v ss =0v this device is manufactured on a cmos process, therefore, generically susceptible to damage by excessive static voltage. failure to observe proper handling and in stallation procedures can cause damage . akm recommends that this device is handle d with appropriate precautions. recommended operation condition s parameter s ymbol conditions m in typ m ax unit operating t emperature ta - 4 0 85 ? c positive s upply voltage (1) v dd 2.375 3.3 3. 8 v (1) power of 3.3v require s to be supplied from a sing le source. a decoupling capacitor of 0.1 ? f for power supply line should be locat ed close to each vdd pin. pin characteristics parameter s ymbol conditions m in typ m ax unit input capacitance c in 4 pf input pullup resistor r pu 51 k input pulldo wn resistor r pd 51 k p ower supply characteristics parameter s ymbol conditions m in typ m ax unit power supply current i dd 11 5 ma esd sensitive device
AK8181H draft - e - 02 feb - 2013 - 5 - dc characteristics (lvcmos/lvttl) all specifications at v dd = 2.375v to 3. 8 v , v ss = 0v, ta: - 4 0 to +85 , unless other wise noted parameter symbol conditions min typ max unit i nput high v oltage v ih vdd = 3.3v 2.0 vdd+0.3 v vdd = 2.5v 1.7 vdd+0.3 v i nput low v oltage v il vdd = 3.3v - 0.3 0.8 v vdd = 2.5v - 0.3 0.7 v input high c urrent clk_sel i ih v in = v dd = 3.8 v 150 a il vin = vss, v dd = 3.8 v - 5 a dc characteristics all specifications at v dd = 2.375v to 3. 8 v , v ss = 0v , ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit input high c urrent pclkx p i ih v in = v dd = 3. 8 v or 2.625v 150 a pclkx n v in = v dd = 3. 8 v or 2.625v 5 a pclkx p i il vin = vss, v dd = 3.8 v or 2.625v - 5 a pclkx n vin = vss, v dd = 3 .8 v or 2.625v - 150 a pp 0.15 1.3 v common m ode input voltage (1) (2) v cmr v ss+0.5 v dd - 0.85 v (1) v il should not be less than - 0.3v . (2) common mode voltage is defined as v ih . dc characteristics (lvpecl) all specifications at v dd = 2.375v to 3. 8 v , v ss = 0v , ta: - 40 to +85 , unless otherwise noted para meter symbol conditions min typ max unit output high voltage (1 ) v oh v dd - 1.4 v dd - 0.9 v output low voltage (1) v ol v dd - 2.0 v dd - 1.7 v peak - to - peak output voltage swing v swing 0.6 1.0 v (1) outputs terminated with 50 to v dd - 2v.
AK8181H feb - 2013 draft - e - 02 - 6 - ac characteristics all specifications at v dd = 2.375v to 3. 8 v or, v ss = 0v, ta: - 40 to +85 , unless otherwise noted all parameters measured at f 70 0mhz unless noted otherwise. the cycle to cycle jitter on the input will equal the jitter on the output. the part does not add jitter. (1) measured from the differential input crossing point to the differential output crossing point. (2) defined as skew between outputs at the same supply voltage and with equal load conditions . measured at the output differential cross points. (3) this parameter is defined in accordance with jedec standard 65. (4) defined as skew between outputs on different devices operating at the same supply voltage s and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. (5) design value. parameter symbol conditions min typ max unit output frequency f out 70 0 mhz propagation delay (1) t pd t.b.d n s output skew (2) (3) t sk(o) 30 ps part - t o - part skew (3 ) (4) t skpp 34 0 ps buffer additive jitter, rms (5) t jit 155 . 5 2mhz (12khz C 20mhz) 0.04 5 ps output rise/fall time (5) t r , t f 20% to 80% 15 0 50 0 p s output duty cycle dc out 47 50 53 %
AK8181H draft - e - 02 feb - 2013 - 7 - figure 1 lvpecl output load figure 2 diffe rential input level ac test circuit figure 3 output skew figure 4 output rise/fall time figure 5 part - to - part skew figure 6 propagation delay figure 7 output duty/ pulse width/ period c l o c k o u t p u t s 8 0 % q x t s k ( o ) q x n q y n q y t r t f 2 0 % 8 0 % 2 0 % v s w i n g
AK8181H feb - 2013 draft - e - 02 - 8 - function table the following table shows the input s /output s clock state configured through the control pins . table 1 : control input functio n t able inputs outputs input to output polarity pclk0/1p pclk0/1n q0:q9 q0n:q 9 n 0 1 l ow h igh differential to differential non inverting 1 0 h igh l ow differential to differential non inverting 0 biased (1) l ow h igh single ended to differential non inv erting 1 biased (1) h igh l ow single ended to differential non inverting biased (1) 0 h igh l ow single ended to differential inverting biased (1) 1 l ow h igh single ended to differential inverting (1) please refer to the application information section, wiri ng the differential input to accept single ended levels . table 2 clock input function table inputs clk_sel selected source 0 pclk0p/n 1 pclk1p/n
AK8181H draft - e - 02 feb - 2013 - 9 - application information wiring the differential input to accept single ende d levels figure.8 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = vdd/2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and vdd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 8 single ended signal dr iving differential input
AK8181H feb - 2013 draft - e - 02 - 10 - package information ? mechanical data : 32 pin lqfp pre liminary 0 b 7 b 0 . 0 5 0 . 1 5 0 . 0 9 0 . 2 0 0 . 2 0 m 0 . 3 7 0 . 0 5 1 8 9 1 6 1 7 2 4 2 5 3 2 7 . 0 0 9 . 0 0 0 . 2 0 9 . 0 0 0 . 2 0 7 . 0 0 0 . 8 0 0 . 6 0 0 . 1 0 1 . 6 0 m a x 1 . 3 5 1 . 4 5 s s 0 . 1 0
AK8181H draft - e - 02 feb - 2013 - 11 - ? marking a: #1 pin index b: part number c: date code (7 digits) (1) akm is the brand name of akm ic s. akm and the logo - - are the brand of akm s ic s and identify that akm continues to offer t he best choice for high performance mixed - signal solution under this brand. ? rohs compliance all integrated circuits form asahi kasei m icrodevices corporation (akm) assembled in lead free packages* are fully compliant (*) rohs compliant products from akm are identified with pb free letter indication on product label posted on the anti - shield bag and boxes. preliminary
AK8181H feb - 2013 draft - e - 02 - 12 - important notice ? t hese products and their specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. ? descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arisin g from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm . as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must t herefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all cl aims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK8181H

	To Download AK8181H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .